For solid-state image pickup devices, a configuration is known in which a photoelectric conversion unit and a peripheral circuit unit separately formed on different substrates are electrically connected through a micro bump. Patent Literature 1 discloses the following configuration. A photoelectric conversion unit is arranged on a first semiconductor substrate, whereas a peripheral circuit for reading out a signal from the photoelectric conversion unit, such as a vertical scanning unit and a horizontal scanning unit, is arranged on a second semiconductor substrate. Leakage current is less problematic for transistors arranged on the second semiconductor substrate than for a pixel unit. Accordingly, gate insulating films of the downsized transistors on the second semiconductor substrate are thinned with a CMOS process.
Patent Literature 1 does not fully discuss amplitude of a pulse for driving a transfer transistor that transfers charge generated in the photoelectric conversion unit. The pulse fed to a gate of the transfer transistor may be desired to have larger amplitude than those fed to other transistors in the pixel unit or transistors in the peripheral circuit because of the following reason.
Current leaking from a channel of the transfer transistor during a charge accumulation period of the photoelectric conversion unit may result in dark current. To prevent the dark current, voltage fed to the gate of the transfer transistor during the charge accumulation period can be set to be lower (higher regarding a PMOS transistor) than off-voltage of the other transistors. Accordingly, a range of the voltage fed to the gate of the transfer transistor is wider than that of the voltage fed to the other transistors in the pixel unit and the transistors in the peripheral circuit.
However, Patent Literature 1 does not disclose a circuit for making the amplitude of the pulse fed to the transfer transistor larger than that of the pulses fed to the other transistors and, thus, does not discuss where to arrange such a circuit. Depending on the arrangement, realization of low power-supply voltage is disturbed.
In view of the foregoing problem, the present invention suppresses dark current from the transfer transistor and lowers power-supply voltage in a second semiconductor substrate at the same time.